Design of Efficient AMBA AHB Arbiter

Authors

Vennapoosa Hemanth Kumar Reddy
MS in VLSI Engineering, Veda IIT, Guntur, AP, India.
Harika Chaparala
SMTS, Invecas, Guntur, AP, India.
Prof. K. Malakondaiah, Director, HOD
Dept of VLSI, Veda IIT, Guntur, AP, India.

Abstract

Many separate IP cores are coupled together with a complicated on-chip bus communication architecture in a typical System-on-Chip (SOC) design. In complicated SOC design, the on-chip bus communication architecture is a major predictor of total performance. AMBA, Wishbone, Core Connect, Avalon, and other connection buses are often used in the industry. AMBA is the most popular of the three because it has a hierarchy of buses, with AHB (Advanced High-Performance Bus) for high-performance peripherals and APB (Advanced Peripheral Bus) for low-performance peripherals. When dealing with several masters seeking to access a single data bus, resolution is a major difficulty in SOC. At such point, an arbiter is crucial. The goal of this research is to develop RTL code for AMBA AHB arbiter and perform STA to improve the timing aspects. The RTL is developed for a generic number of masters, allowing us to add and remove them as needed. For Synthesis and STA (Static timing analysis) of the design, I have considered mylib.db as TL (Technology library). And finally, I generated the netlist. The design architecture is written using Verilog HDL code and STA is done using DC (Design compiler from Synopsys) tools. The architecture is modelled and synthesized using RTL (Register Transfer Level) abstraction.